VLSI LAYOUT DESIGN OF A SYSTOLIC MULTIPLIER UNIT FOR 2'S COMPLEMENT NUMBERS.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original language	English
Title of host publication	Unknown Host Publication Title
Publisher	IEEE
Pages	354-358
Number of pages	5
ISBN (Print)	0818606428
State	Published - 1985
Externally published	Yes

ASJC Scopus Subject Areas

@inproceedings{b52710d0bddf4845b6136fa9183bec61,

title = "VLSI LAYOUT DESIGN OF A SYSTOLIC MULTIPLIER UNIT FOR 2'S COMPLEMENT NUMBERS.",

author = "Hurson, \{A. R.\} and B. Shirazi and Pakzad, \{S. H.\}",

year = "1985",

language = "English",

isbn = "0818606428",

publisher = "IEEE",

pages = "354--358",

booktitle = "Unknown Host Publication Title",

}

TY - GEN

T1 - VLSI LAYOUT DESIGN OF A SYSTOLIC MULTIPLIER UNIT FOR 2'S COMPLEMENT NUMBERS.

AU - Hurson, A. R.

AU - Shirazi, B.

AU - Pakzad, S. H.

PY - 1985

Y1 - 1985

UR - https://www.scopus.com/pages/publications/0022286064

UR - https://www.scopus.com/pages/publications/0022286064#tab=citedBy

M3 - Conference contribution

AN - SCOPUS:0022286064

SN - 0818606428

SP - 354

EP - 358

BT - Unknown Host Publication Title

PB - IEEE

ER -