Abstract
A low impedance power distribution network (PDN) is essential for the functionality of high speed printed circuit boards. A pre-layout impedance calculation can avoid time consuming changes on the design during post-layout stage. Design curves for inductance estimation are convenient to use in pre-layout stage. However, the high density voids on the power plane, which is caused by the anti-pads, are not considered in those design curves. This short paper discussed the extra inductance caused by the anti-pads, in two common situations.
| Original language | American English |
|---|---|
| Journal | Proceedings of the 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (2017, Haining, China) |
| DOIs | |
| State | Published - Dec 1 2017 |
Keywords
- Design curves
- Impedance calculations
- Inductance
- Inductance estimations
- Low impedance
- Plane-pair PEEC
- Power distribution network
- Power integrity
- Power planes
- Printed circuit boards
Disciplines
- Electrical and Computer Engineering
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