Abstract
This paper presents an impedance-matching network design with numerical modeling of the parasitic effects. A modeling tool CEMPIE (a Circuit Extraction approach based on a Mixed Potential Integral Equation formulation) is used to model the hoard-level parasitics of surface mount technology (SMT) resistors for impedance-matching networks. A 3-layer design of impedance-matching network with 0402 SMT resistors is implemented according to the modeling results. And its performance is demonstrated.
| Original language | American English |
|---|---|
| Pages (from-to) | 984-987 |
| Number of pages | 4 |
| Journal | Proceedings of the IEEE International Symposium on Electromagnetic Compatibility, 2004 |
| DOIs | |
| State | Published - Aug 1 2004 |
| Event | 2004 International Symposium on Electromagnetic Compatibility, EMC 2004 - Santa Clara, CA, United States Duration: Aug 9 2004 → Aug 13 2004 |
ASJC Scopus Subject Areas
- Condensed Matter Physics
- Electrical and Electronic Engineering
Keywords
- CEMPIE
- Impedance-matching network
- Parasitics
- PEEC
Disciplines
- Electrical and Computer Engineering
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