Test Generation for Combinational Logic Circuits using Information Theory

Paul D. Stigall; Y. M. Erten

doi:10.1016/0045-7906(86)90019-4

Test Generation for Combinational Logic Circuits using Information Theory

Paul D. Stigall
, Y. M. Erten

Missouri University of Science and Technology

Research output: Contribution to journal › Article › peer-review

Abstract

Application of Probability and Information Theory to Test Pattern Generation for Combinational Logic Circuits is Investigated. It is Verified that Choosing the Input Probability to Maximize the Output Information Reduced to a Minimum the Number of Random Patterns to Be Generated to Detect All the Faults in the Circuit. This Result is Tested on Three Examples using a Logic Simulator. the Simulator Was Implemented using a TRS-80 Color Computer with 16K Memory, and the Use of Microcomputers in Fault Detection is Discussed. This Work Considers Only Combinational Logic Circuits and Single Stuck-At Type Faults. © 1986.

Original language	American English
Journal	Computers and Electrical Engineering
Volume	12
DOIs	https://doi.org/10.1016/0045-7906(86)90019-4
State	Published - Jan 1 1986

Disciplines

Electrical and Computer Engineering

Access to Document

10.1016/0045-7906(86)90019-4License: Unspecified

https://doi.org/10.1016/0045-7906(86)90019-4

Cite this

@article{5d98a0dccaa5415eaf3fe34caf851a35,

title = "Test Generation for Combinational Logic Circuits using Information Theory",

abstract = " Application of Probability and Information Theory to Test Pattern Generation for Combinational Logic Circuits is Investigated. It is Verified that Choosing the Input Probability to Maximize the Output Information Reduced to a Minimum the Number of Random Patterns to Be Generated to Detect All the Faults in the Circuit. This Result is Tested on Three Examples using a Logic Simulator. the Simulator Was Implemented using a TRS-80 Color Computer with 16K Memory, and the Use of Microcomputers in Fault Detection is Discussed. This Work Considers Only Combinational Logic Circuits and Single Stuck-At Type Faults. {\textcopyright} 1986.",

author = "Stigall, \{Paul D.\} and Erten, \{Y. M.\}",

year = "1986",

month = jan,

day = "1",

doi = "10.1016/0045-7906(86)90019-4",

language = "American English",

volume = "12",

journal = "Computers and Electrical Engineering",

}

TY - JOUR

T1 - Test Generation for Combinational Logic Circuits using Information Theory

AU - Stigall, Paul D.

AU - Erten, Y. M.

PY - 1986/1/1

Y1 - 1986/1/1

N2 - Application of Probability and Information Theory to Test Pattern Generation for Combinational Logic Circuits is Investigated. It is Verified that Choosing the Input Probability to Maximize the Output Information Reduced to a Minimum the Number of Random Patterns to Be Generated to Detect All the Faults in the Circuit. This Result is Tested on Three Examples using a Logic Simulator. the Simulator Was Implemented using a TRS-80 Color Computer with 16K Memory, and the Use of Microcomputers in Fault Detection is Discussed. This Work Considers Only Combinational Logic Circuits and Single Stuck-At Type Faults. © 1986.

AB - Application of Probability and Information Theory to Test Pattern Generation for Combinational Logic Circuits is Investigated. It is Verified that Choosing the Input Probability to Maximize the Output Information Reduced to a Minimum the Number of Random Patterns to Be Generated to Detect All the Faults in the Circuit. This Result is Tested on Three Examples using a Logic Simulator. the Simulator Was Implemented using a TRS-80 Color Computer with 16K Memory, and the Use of Microcomputers in Fault Detection is Discussed. This Work Considers Only Combinational Logic Circuits and Single Stuck-At Type Faults. © 1986.

UR - https://scholarsmine.mst.edu/ele_comeng_facwork/4779

UR - https://doi.org/10.1016/0045-7906(86)90019-4

U2 - 10.1016/0045-7906(86)90019-4

DO - 10.1016/0045-7906(86)90019-4

M3 - Article

VL - 12

JO - Computers and Electrical Engineering

JF - Computers and Electrical Engineering

ER -

Test Generation for Combinational Logic Circuits using Information Theory

Abstract

Disciplines

Access to Document

Other files and links

Fingerprint

Cite this