Sensitivity Analysis of Local Soldermask and Coverlay in High Speed Transimission Lines for DDR5 Applications to Reduce FEXT

Zhu Lin; Xin Cao; Qiang Ming Cai; Yinglei Ren; Xiaoning Ye; Jun Fan

doi:10.1109/EMCSI38923.2020.9191478

Sensitivity Analysis of Local Soldermask and Coverlay in High Speed Transimission Lines for DDR5 Applications to Reduce FEXT

Zhu Lin
, Xin Cao
, Qiang Ming Cai
, Yinglei Ren
, Xiaoning Ye
, Jun Fan

Electrical and Computer Engineering

Southwest University of Science and Technology
Intel

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original language	English
Title of host publication	2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	586-590
Number of pages	5
ISBN (Electronic)	9781728174303
DOIs	https://doi.org/10.1109/EMCSI38923.2020.9191478
State	Published - Jul 2020
Event	2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020 - Reno, United States Duration: Jul 28 2020 → Aug 28 2020

Publication series

Name	2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020

Conference

Conference	2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020
Country/Territory	United States
City	Reno
Period	7/28/20 → 8/28/20

ASJC Scopus Subject Areas

Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Radiation
Signal Processing
Information Systems and Management

Keywords

Coverlay
DDR5
Far-end crosstalk (FEXT)
microstrip line
printed circuit board (PCB)
soldermask

Access to Document

10.1109/EMCSI38923.2020.9191478

Cite this

Lin, Z., Cao, X., Cai, Q. M., Ren, Y., Ye, X., & Fan, J. (2020). Sensitivity Analysis of Local Soldermask and Coverlay in High Speed Transimission Lines for DDR5 Applications to Reduce FEXT. In 2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020 (pp. 586-590). Article 9191478 (2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EMCSI38923.2020.9191478

Sensitivity Analysis of Local Soldermask and Coverlay in High Speed Transimission Lines for DDR5 Applications to Reduce FEXT. / Lin, Zhu; Cao, Xin; Cai, Qiang Ming et al.
2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 586-590 9191478 (2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lin, Z, Cao, X, Cai, QM, Ren, Y, Ye, X & Fan, J 2020, Sensitivity Analysis of Local Soldermask and Coverlay in High Speed Transimission Lines for DDR5 Applications to Reduce FEXT. in 2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020., 9191478, 2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020, Institute of Electrical and Electronics Engineers Inc., pp. 586-590, 2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020, Reno, United States, 7/28/20. https://doi.org/10.1109/EMCSI38923.2020.9191478

Lin Z, Cao X, Cai QM, Ren Y, Ye X, Fan J. Sensitivity Analysis of Local Soldermask and Coverlay in High Speed Transimission Lines for DDR5 Applications to Reduce FEXT. In 2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 586-590. 9191478. (2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020). doi: 10.1109/EMCSI38923.2020.9191478

Lin, Zhu ; Cao, Xin ; Cai, Qiang Ming et al. / Sensitivity Analysis of Local Soldermask and Coverlay in High Speed Transimission Lines for DDR5 Applications to Reduce FEXT. 2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 586-590 (2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020).

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title = "Sensitivity Analysis of Local Soldermask and Coverlay in High Speed Transimission Lines for DDR5 Applications to Reduce FEXT",

keywords = "Coverlay, DDR5, Far-end crosstalk (FEXT), microstrip line, printed circuit board (PCB), soldermask",

author = "Zhu Lin and Xin Cao and Cai, \{Qiang Ming\} and Yinglei Ren and Xiaoning Ye and Jun Fan",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020 ; Conference date: 28-07-2020 Through 28-08-2020",

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KW - microstrip line

KW - printed circuit board (PCB)

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M3 - Conference contribution

AN - SCOPUS:85091821291

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Sensitivity Analysis of Local Soldermask and Coverlay in High Speed Transimission Lines for DDR5 Applications to Reduce FEXT

Publication series

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ASJC Scopus Subject Areas

Keywords

Access to Document

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