Regressive Testing for System-on-Chip with Unknown-Good-Yield

This paper presents a testing method for electronic devices with no a-priori yield information. This problem is referred to as Unknown-Good-Yield (UKGY) problem. The UKGY problem of Systems-on-Chip (SoC) is discussed in this paper as SoCs are in general built with embedded Intellectual Property (IP) Cores, each of which procured from IP providers with no information on Known-Good-Yield (KGY). In general, partial testing is a practical choice for assuring the yield of the product under the stringent time-to-market requirement in today's high density/complexity electronic devices such as SoC built with deep submicron or nano technology. Therefore, efficient and effective sampling technique is a key to the success of high confidence testing. An Experimental Characterization-based Testing (referred to as ET) method for SoC has been proposed prior to this work, in which a stratified sampling method was employed based on environmental-based characterization and experimental design technique to enhance the confidence level of the estimation of yield. The proposed testing method, referred to as Regressive Testing (RegT), in this paper exploits another way around by using parameters (referred to as Assistant Variables (AV) free from UKGY that determines the criteria to sample and test SoCs, and employs the regression analysis method to evaluate the yield with regard to confidence interval. A numerical simulation is conducted to demonstrate the efficiency and effectiveness of the proposed RegT in comparison with generic random testing method.