Probabilistic Analysis of Design Mapping in Asynchronous Nanowire Crossbar Architecture

There have been numerous nanowire crossbar architectures proposed till date and they are envisioned as clockdriven. To deal with numerous issues caused by clocking, a new asynchronous architecture based on Null Convention Logic (NCL) has been recently proposed, resulting in the removal of the clock circuit overhead from the crossbar architecture. The proposed architecture is easier to be manufactured and all clocking-related issues are also eliminated. Even though the proposed architecture has considerable merits over its clocked counterpart, it is still prone to defects due to nondeterministic nature of nanoscale assembly and the defect density is directly proportional to the density of nanowires in the architecture. Hence a number of ways are being examined to effectively avoid the defects to make the architecture defect tolerant. Considering the fact that the nano crossbar architecture has a large number of defects due to manufacturing constraints and its extremely small size, the variations in mapping probabilities with certain factors, such as defect rate, size of crossbar matrix, and type of threshold gate are numerically measured to get an optimized design for resilient clock-free nanowire crossbar systems.