Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with H-Hot Addressing Scheme

Shanrui Zhang; Minsu Choi; Nohpill Park

doi:10.1109/DFTVS.2004.1347860

Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with H-Hot Addressing Scheme

Shanrui Zhang
, Minsu Choi
, Nohpill Park

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

With molecular-scale materials, devices and fabrication techniques recently being developed, high-density computing systems in the nanometer domain emerge. An array-based nanoarchitecture has been recently proposed based on nanowires such as carbon nanotubes (CNTs) and silicon nanowires (SiNWs). High-density nanoarray-based systems consisting of nanometer-scale elements are likely to have many imperfections; thus, defect-tolerance is considered one of the most significant challenges. In this paper we propose a probabilistic yield model for the array-based nanoarchitecture. The proposed yield model can be used (1) to accurately estimate the raw and net array densities, and (2) to design and optimize more defect and fault-tolerant systems based on the array-based nanoarchitecture. As a case study, the proposed yield model is applied to the defect-tolerant addressing scheme called h-hot addressing and simulation results are discussed.

Original language	American English
Journal	Proceedings of the 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (2004, Cannes, France)
DOIs	https://doi.org/10.1109/DFTVS.2004.1347860
State	Published - Oct 1 2004

Keywords

Array-Based Nanoarchitecture
C
CNT
Carbon Nanotubes
Circuit Simulation
Computer Architecture
Defect-Tolerance
Defect-Tolerant Addressing Scheme
Defect-Tolerant Systems
Elemental Semiconductors
FET-Based Nanoarray Architecture
Fabrication Techniques
Fault-Tolerant Systems
H-Hot Addressing Scheme
High-Density Computing Systems
Integrated Circuit Modelling
Integrated Circuit Technology
Integrated Circuit Yield
Molecular-Scale Materials
Nanoelectronics
Nanometer-Scale Elements
Nanotube Devices
Nanowires
Net Array Densities
Probabilistic Yield Model
Raw Array Densities
Si
SiNW
Silicon
Silicon Nanowires
Simulation
Yield Modeling

Disciplines

Electrical and Computer Engineering

Access to Document

10.1109/DFTVS.2004.1347860License: Unspecified

Modeling Yield of Carbon-Nanotube Silicon-Nanowire FET-Based NanoFinal published version, 1.31 MBLicense: Unspecified

Cite this

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title = "Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with H-Hot Addressing Scheme",

abstract = " With molecular-scale materials, devices and fabrication techniques recently being developed, high-density computing systems in the nanometer domain emerge. An array-based nanoarchitecture has been recently proposed based on nanowires such as carbon nanotubes (CNTs) and silicon nanowires (SiNWs). High-density nanoarray-based systems consisting of nanometer-scale elements are likely to have many imperfections; thus, defect-tolerance is considered one of the most significant challenges. In this paper we propose a probabilistic yield model for the array-based nanoarchitecture. The proposed yield model can be used (1) to accurately estimate the raw and net array densities, and (2) to design and optimize more defect and fault-tolerant systems based on the array-based nanoarchitecture. As a case study, the proposed yield model is applied to the defect-tolerant addressing scheme called h-hot addressing and simulation results are discussed.",

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author = "Shanrui Zhang and Minsu Choi and Nohpill Park",

year = "2004",

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doi = "10.1109/DFTVS.2004.1347860",

language = "American English",

journal = "Proceedings of the 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (2004, Cannes, France)",

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AU - Zhang, Shanrui

AU - Choi, Minsu

AU - Park, Nohpill

PY - 2004/10/1

Y1 - 2004/10/1

N2 - With molecular-scale materials, devices and fabrication techniques recently being developed, high-density computing systems in the nanometer domain emerge. An array-based nanoarchitecture has been recently proposed based on nanowires such as carbon nanotubes (CNTs) and silicon nanowires (SiNWs). High-density nanoarray-based systems consisting of nanometer-scale elements are likely to have many imperfections; thus, defect-tolerance is considered one of the most significant challenges. In this paper we propose a probabilistic yield model for the array-based nanoarchitecture. The proposed yield model can be used (1) to accurately estimate the raw and net array densities, and (2) to design and optimize more defect and fault-tolerant systems based on the array-based nanoarchitecture. As a case study, the proposed yield model is applied to the defect-tolerant addressing scheme called h-hot addressing and simulation results are discussed.

AB - With molecular-scale materials, devices and fabrication techniques recently being developed, high-density computing systems in the nanometer domain emerge. An array-based nanoarchitecture has been recently proposed based on nanowires such as carbon nanotubes (CNTs) and silicon nanowires (SiNWs). High-density nanoarray-based systems consisting of nanometer-scale elements are likely to have many imperfections; thus, defect-tolerance is considered one of the most significant challenges. In this paper we propose a probabilistic yield model for the array-based nanoarchitecture. The proposed yield model can be used (1) to accurately estimate the raw and net array densities, and (2) to design and optimize more defect and fault-tolerant systems based on the array-based nanoarchitecture. As a case study, the proposed yield model is applied to the defect-tolerant addressing scheme called h-hot addressing and simulation results are discussed.

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ER -

Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with H-Hot Addressing Scheme

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