Modeling and Design of Buried Capacitances for Power Distribution Networks on Multilayer Printed Circuit Board

The engineering of the power delivery network is becoming a fundamental issue in the design of high speed digital systems on printed circuit boards (PCB). In fact, providing the required noise free voltage level to the different integrated circuits (IC) on a PCB system allows achieving the correct functioning of the systems and the desired performance as well. Several decoupling strategies can be employed for this crucial design goal, i.e., local decoupling, global decoupling [1,2] and buried capacitances. Due to improvements in the manufactory processes and cost reduction, the employment of buried capacitance as a decoupling strategy is becoming a more viable solution, being a buried capacitance just a pair of solid planes separated by distances on the order of few mils or less, therefore the less complicated solution.