Extraction of the Parameters of the Coupling Capacitance Hysteresis Cycle for TSV Transient Modeling

Stefano Piersanti; E. Pellegrino; Francesco de Paulis; Antonio Orlandi; Joungho Kim; Jun Fan

doi:10.1109/ISEMC.2016.7571682

Extraction of the Parameters of the Coupling Capacitance Hysteresis Cycle for TSV Transient Modeling

Stefano Piersanti
, E. Pellegrino
, Francesco de Paulis
, Antonio Orlandi
, Joungho Kim
, Jun Fan

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

The paper deals with the extraction, from the measurement, of the parameters needed to identify in time domain the hysteretic behavior of the coupling capacitance of through silicon via (TSV). The algorithm is developed in such a way that the equivalent capacitance model can be implemented into standard circuit simulators. Results showing the effect of the hysteresis on the crosstalk among TSV and IC active devices are shown and discussed.

Original language	American English
Journal	IEEE International Symposium on Electromagnetic Compatibility (2016, Ottawa, Canada)
DOIs	https://doi.org/10.1109/ISEMC.2016.7571682
State	Published - Jul 1 2016

Keywords

Active devices
Capacitance
Circuit simulation
Dielectric hysteresis
Electromagnetic compatibility
Electronics packaging
Equivalent circuit model
Equivalent circuits
Extraction
Hysteresis
Integrated circuit interconnects
Integrated circuit manufacture
Nonlinear effect
Reconfigurable hardware
Signal Integrity
Three dimensional integrated circuits
Through silicon vias
Time domain

Disciplines

Electrical and Computer Engineering
Numerical Analysis and Scientific Computing

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10.1109/ISEMC.2016.7571682License: Unspecified

https://doi.org/10.1109/ISEMC.2016.7571682

Cite this

@article{909c3dc5a8464e829591e3fae7ef037a,

title = "Extraction of the Parameters of the Coupling Capacitance Hysteresis Cycle for TSV Transient Modeling",

abstract = " The paper deals with the extraction, from the measurement, of the parameters needed to identify in time domain the hysteretic behavior of the coupling capacitance of through silicon via (TSV). The algorithm is developed in such a way that the equivalent capacitance model can be implemented into standard circuit simulators. Results showing the effect of the hysteresis on the crosstalk among TSV and IC active devices are shown and discussed.",

keywords = "Active devices, Capacitance, Circuit simulation, Dielectric hysteresis, Electromagnetic compatibility, Electronics packaging, Equivalent circuit model, Equivalent circuits, Extraction, Hysteresis, Integrated circuit interconnects, Integrated circuit manufacture, Nonlinear effect, Reconfigurable hardware, Signal Integrity, Three dimensional integrated circuits, Through silicon vias, Time domain",

author = "Stefano Piersanti and E. Pellegrino and \{de Paulis\}, Francesco and Antonio Orlandi and Joungho Kim and Jun Fan",

year = "2016",

month = jul,

day = "1",

doi = "10.1109/ISEMC.2016.7571682",

language = "American English",

journal = "IEEE International Symposium on Electromagnetic Compatibility (2016, Ottawa, Canada)",

}

TY - JOUR

T1 - Extraction of the Parameters of the Coupling Capacitance Hysteresis Cycle for TSV Transient Modeling

AU - Piersanti, Stefano

AU - Pellegrino, E.

AU - de Paulis, Francesco

AU - Orlandi, Antonio

AU - Kim, Joungho

AU - Fan, Jun

PY - 2016/7/1

Y1 - 2016/7/1

N2 - The paper deals with the extraction, from the measurement, of the parameters needed to identify in time domain the hysteretic behavior of the coupling capacitance of through silicon via (TSV). The algorithm is developed in such a way that the equivalent capacitance model can be implemented into standard circuit simulators. Results showing the effect of the hysteresis on the crosstalk among TSV and IC active devices are shown and discussed.

AB - The paper deals with the extraction, from the measurement, of the parameters needed to identify in time domain the hysteretic behavior of the coupling capacitance of through silicon via (TSV). The algorithm is developed in such a way that the equivalent capacitance model can be implemented into standard circuit simulators. Results showing the effect of the hysteresis on the crosstalk among TSV and IC active devices are shown and discussed.

KW - Active devices

KW - Capacitance

KW - Circuit simulation

KW - Dielectric hysteresis

KW - Electromagnetic compatibility

KW - Electronics packaging

KW - Equivalent circuit model

KW - Equivalent circuits

KW - Extraction

KW - Hysteresis

KW - Integrated circuit interconnects

KW - Integrated circuit manufacture

KW - Nonlinear effect

KW - Reconfigurable hardware

KW - Signal Integrity

KW - Three dimensional integrated circuits

KW - Through silicon vias

KW - Time domain

UR - https://scholarsmine.mst.edu/ele_comeng_facwork/2039

UR - https://doi.org/10.1109/ISEMC.2016.7571682

U2 - 10.1109/ISEMC.2016.7571682

DO - 10.1109/ISEMC.2016.7571682

M3 - Article

JO - IEEE International Symposium on Electromagnetic Compatibility (2016, Ottawa, Canada)

JF - IEEE International Symposium on Electromagnetic Compatibility (2016, Ottawa, Canada)

ER -

Extraction of the Parameters of the Coupling Capacitance Hysteresis Cycle for TSV Transient Modeling

Abstract

Keywords

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