Extracting CAD Models for Quantifying Noise Coupling Between Vias in PCB Layouts

Shaofeng Luan; Jun Fan; W. Liu; Fengchao Xiao; James L. Knighten; Norman W. Smith; Ray Alexander; Jim Nadolny; Yoshio Kami; James L. Drewniak

doi:10.1109/ECTC.2002.1008118

Extracting CAD Models for Quantifying Noise Coupling Between Vias in PCB Layouts

Shaofeng Luan
, Jun Fan
, W. Liu
, Fengchao Xiao
, James L. Knighten
, Norman W. Smith
, Ray Alexander
, Jim Nadolny
, Yoshio Kami
, James L. Drewniak

Research output: Contribution to journal › Article › peer-review

Abstract

A method to extract a lumped element prototype SPICE model is used to study noise coupling between non-parallel traces on a PCB. The parameters in this model are extracted using a PEEC-like approach, a Circuit Extraction approach based on a Mixed-Potential Integral Equation formulation (CEMPIE). Without large numbers of unknowns, the SPICE model saves computation time. Also, it is easy to incorporate into system SPICE net list to acquire the system simulation result considering the coupling between traces on the printed circuit board (PCB). A representative case is studied, and the comparison of measurements, CEMPIE simulation, and SPICE modeling are given.

Original language	American English
Pages (from-to)	343-346
Number of pages	4
Journal	Proceedings of the 52nd IEEE Electronic Components and Technology Conference (2002, San Diego, CA)
DOIs	https://doi.org/10.1109/ECTC.2002.1008118
State	Published - May 1 2002

Keywords

CAD Model
CEMPIE Simulation
PCB Layout
PEEC
SPICE
Circuit Extraction
Circuit Layout CAD
Circuit Noise
Equivalent Circuits
Integral Equations
Lumped Element SPICE Model
Mixed-Potential Integral Equation
Noise Coupling
Nonparallel Traces
Parameter Extraction
Printed Circuit Layout
Via
Computer Aided Design
Computer Simulation
Electric Lines
Mathematical Models
Matrix Algebra
Spurious Signal Noise
Quantifying Noise
Printed Circuit Boards

Disciplines

Electrical and Computer Engineering

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10.1109/ECTC.2002.1008118License: CC BY

Extracting CAD Models for Quantifying Noise Coupling Between ViasFinal published version, 419 KBLicense: CC BY

Cite this

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title = "Extracting CAD Models for Quantifying Noise Coupling Between Vias in PCB Layouts",

abstract = " A method to extract a lumped element prototype SPICE model is used to study noise coupling between non-parallel traces on a PCB. The parameters in this model are extracted using a PEEC-like approach, a Circuit Extraction approach based on a Mixed-Potential Integral Equation formulation (CEMPIE). Without large numbers of unknowns, the SPICE model saves computation time. Also, it is easy to incorporate into system SPICE net list to acquire the system simulation result considering the coupling between traces on the printed circuit board (PCB). A representative case is studied, and the comparison of measurements, CEMPIE simulation, and SPICE modeling are given.",

keywords = "CAD Model, CEMPIE Simulation, PCB Layout, PEEC, SPICE, Circuit Extraction, Circuit Layout CAD, Circuit Noise, Equivalent Circuits, Integral Equations, Lumped Element SPICE Model, Mixed-Potential Integral Equation, Noise Coupling, Nonparallel Traces, Parameter Extraction, Printed Circuit Layout, Via, Computer Aided Design, Computer Simulation, Electric Lines, Mathematical Models, Matrix Algebra, Spurious Signal Noise, Quantifying Noise, Printed Circuit Boards",

author = "Shaofeng Luan and Jun Fan and W. Liu and Fengchao Xiao and Knighten, \{James L.\} and Smith, \{Norman W.\} and Ray Alexander and Jim Nadolny and Yoshio Kami and Drewniak, \{James L.\}",

year = "2002",

month = may,

day = "1",

doi = "10.1109/ECTC.2002.1008118",

language = "American English",

pages = "343--346",

journal = "Proceedings of the 52nd IEEE Electronic Components and Technology Conference (2002, San Diego, CA)",

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AU - Luan, Shaofeng

AU - Fan, Jun

AU - Liu, W.

AU - Xiao, Fengchao

AU - Knighten, James L.

AU - Smith, Norman W.

AU - Alexander, Ray

AU - Nadolny, Jim

AU - Kami, Yoshio

AU - Drewniak, James L.

PY - 2002/5/1

Y1 - 2002/5/1

N2 - A method to extract a lumped element prototype SPICE model is used to study noise coupling between non-parallel traces on a PCB. The parameters in this model are extracted using a PEEC-like approach, a Circuit Extraction approach based on a Mixed-Potential Integral Equation formulation (CEMPIE). Without large numbers of unknowns, the SPICE model saves computation time. Also, it is easy to incorporate into system SPICE net list to acquire the system simulation result considering the coupling between traces on the printed circuit board (PCB). A representative case is studied, and the comparison of measurements, CEMPIE simulation, and SPICE modeling are given.

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KW - Mixed-Potential Integral Equation

KW - Noise Coupling

KW - Nonparallel Traces

KW - Parameter Extraction

KW - Printed Circuit Layout

KW - Via

KW - Computer Aided Design

KW - Computer Simulation

KW - Electric Lines

KW - Mathematical Models

KW - Matrix Algebra

KW - Spurious Signal Noise

KW - Quantifying Noise

KW - Printed Circuit Boards

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JO - Proceedings of the 52nd IEEE Electronic Components and Technology Conference (2002, San Diego, CA)

JF - Proceedings of the 52nd IEEE Electronic Components and Technology Conference (2002, San Diego, CA)

ER -

Extracting CAD Models for Quantifying Noise Coupling Between Vias in PCB Layouts

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Keywords

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