Design and Modeling for Chip-to-Chip Communication at 20 Gbps

Jianmin Zhang; Qinghua B. Chen; Kelvin Qiu; Antonio Ciccomancini Scogna; Martin Schauer; Gerardo Romo; James L. Drewniak; Antonio Orlandi

doi:10.1109/ISEMC.2010.5711320

Design and Modeling for Chip-to-Chip Communication at 20 Gbps

Jianmin Zhang
, Qinghua B. Chen
, Kelvin Qiu
, Antonio Ciccomancini Scogna
, Martin Schauer
, Gerardo Romo
, James L. Drewniak
, Antonio Orlandi

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling and correlation for PCBs (Printed Circuit Boards) with FR4 substrate materials. The entire channel under investigation includes two packages, a 21-layer ceramic and a 12-layer organic, and a 22-layer PCB. A probing station, microprobes and a VNA are used to measure the entire channel S-parameters and the measurement is correlated to the simulation up to 20 GHz. Extended study for the channel with low loss PCB substrate material is simulated. Time-domain eye comparisons for the FR4 channel, low loss channel, and the FR4 channel with equalization are given. A general design rule as well as new technologies for the high-speed channel design at 20 Gbps and beyond are discussed and given in the conclusion.

Original language	American English
Journal	Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (2010, Fort Lauderdale, FL)
DOIs	https://doi.org/10.1109/ISEMC.2010.5711320
State	Published - Jul 1 2010

Keywords

Chip-to-Chip Communications
Design
Design And Modeling
Design Rules
Electromagnetic Compatibility
Electromagnetism
Electronic Equipment Manufacture
FR4 Substrates
High-Speed Channels
Low Loss
Micro-Probes
New Technologies
Printed Circuit Boards
Printed Circuit Design
S-Parameters
Scattering Parameters
Substrate Material
Time Domain

Disciplines

Electrical and Computer Engineering

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10.1109/ISEMC.2010.5711320License: Unspecified

https://doi.org/10.1109/ISEMC.2010.5711320

Cite this

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title = "Design and Modeling for Chip-to-Chip Communication at 20 Gbps",

abstract = " This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling and correlation for PCBs (Printed Circuit Boards) with FR4 substrate materials. The entire channel under investigation includes two packages, a 21-layer ceramic and a 12-layer organic, and a 22-layer PCB. A probing station, microprobes and a VNA are used to measure the entire channel S-parameters and the measurement is correlated to the simulation up to 20 GHz. Extended study for the channel with low loss PCB substrate material is simulated. Time-domain eye comparisons for the FR4 channel, low loss channel, and the FR4 channel with equalization are given. A general design rule as well as new technologies for the high-speed channel design at 20 Gbps and beyond are discussed and given in the conclusion.",

keywords = "Chip-to-Chip Communications, Design, Design And Modeling, Design Rules, Electromagnetic Compatibility, Electromagnetism, Electronic Equipment Manufacture, FR4 Substrates, High-Speed Channels, Low Loss, Micro-Probes, New Technologies, Printed Circuit Boards, Printed Circuit Design, S-Parameters, Scattering Parameters, Substrate Material, Time Domain",

author = "Jianmin Zhang and Chen, \{Qinghua B.\} and Kelvin Qiu and Scogna, \{Antonio Ciccomancini\} and Martin Schauer and Gerardo Romo and Drewniak, \{James L.\} and Antonio Orlandi",

year = "2010",

month = jul,

day = "1",

doi = "10.1109/ISEMC.2010.5711320",

language = "American English",

journal = "Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (2010, Fort Lauderdale, FL)",

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AU - Zhang, Jianmin

AU - Chen, Qinghua B.

AU - Qiu, Kelvin

AU - Scogna, Antonio Ciccomancini

AU - Schauer, Martin

AU - Romo, Gerardo

AU - Drewniak, James L.

AU - Orlandi, Antonio

PY - 2010/7/1

Y1 - 2010/7/1

N2 - This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling and correlation for PCBs (Printed Circuit Boards) with FR4 substrate materials. The entire channel under investigation includes two packages, a 21-layer ceramic and a 12-layer organic, and a 22-layer PCB. A probing station, microprobes and a VNA are used to measure the entire channel S-parameters and the measurement is correlated to the simulation up to 20 GHz. Extended study for the channel with low loss PCB substrate material is simulated. Time-domain eye comparisons for the FR4 channel, low loss channel, and the FR4 channel with equalization are given. A general design rule as well as new technologies for the high-speed channel design at 20 Gbps and beyond are discussed and given in the conclusion.

AB - This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling and correlation for PCBs (Printed Circuit Boards) with FR4 substrate materials. The entire channel under investigation includes two packages, a 21-layer ceramic and a 12-layer organic, and a 22-layer PCB. A probing station, microprobes and a VNA are used to measure the entire channel S-parameters and the measurement is correlated to the simulation up to 20 GHz. Extended study for the channel with low loss PCB substrate material is simulated. Time-domain eye comparisons for the FR4 channel, low loss channel, and the FR4 channel with equalization are given. A general design rule as well as new technologies for the high-speed channel design at 20 Gbps and beyond are discussed and given in the conclusion.

KW - Chip-to-Chip Communications

KW - Design

KW - Design And Modeling

KW - Design Rules

KW - Electromagnetic Compatibility

KW - Electromagnetism

KW - Electronic Equipment Manufacture

KW - FR4 Substrates

KW - High-Speed Channels

KW - Low Loss

KW - Micro-Probes

KW - New Technologies

KW - Printed Circuit Boards

KW - Printed Circuit Design

KW - S-Parameters

KW - Scattering Parameters

KW - Substrate Material

KW - Time Domain

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M3 - Article

JO - Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (2010, Fort Lauderdale, FL)

JF - Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (2010, Fort Lauderdale, FL)

ER -

Design and Modeling for Chip-to-Chip Communication at 20 Gbps

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