Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz

Zhekun Peng; Junyong Park; Sathvika Bandi; Santosh Pappu; Srinivas Venkataraman; Xu Wang; Granthana Ranzaswamy; Dong Hyun Kim

doi:10.1109/EPEPS61853.2024.10754397

Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz

Zhekun Peng
, Junyong Park
, Sathvika Bandi
, Santosh Pappu
, Srinivas Venkataraman
, Xu Wang
, Granthana Ranzaswamy
, Dong Hyun Kim

Electrical and Computer Engineering

Missouri University of Science and Technology
Meta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original language	English
Title of host publication	33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350351231
DOIs	https://doi.org/10.1109/EPEPS61853.2024.10754397
State	Published - 2024
Event	33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024 - Toronto, Canada Duration: Oct 6 2024 → Oct 9 2024

Publication series

Name	33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024

Conference

Conference	33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024
Country/Territory	Canada
City	Toronto
Period	10/6/24 → 10/9/24

ASJC Scopus Subject Areas

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Electronic, Optical and Magnetic Materials
Instrumentation

Keywords

2D cross section analysis
ASIC package substrate interconnects
cascaded S-parameters

Access to Document

10.1109/EPEPS61853.2024.10754397

Cite this

Peng, Z., Park, J., Bandi, S., Pappu, S., Venkataraman, S., Wang, X., Ranzaswamy, G., & Kim, D. H. (2024). Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz. In 33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024 (33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EPEPS61853.2024.10754397

Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz. / Peng, Zhekun; Park, Junyong; Bandi, Sathvika et al.
33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024. Institute of Electrical and Electronics Engineers Inc., 2024. (33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Peng, Z, Park, J, Bandi, S, Pappu, S, Venkataraman, S, Wang, X, Ranzaswamy, G & Kim, DH 2024, Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz. in 33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024. 33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024, Institute of Electrical and Electronics Engineers Inc., 33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024, Toronto, Canada, 10/6/24. https://doi.org/10.1109/EPEPS61853.2024.10754397

Peng Z, Park J, Bandi S, Pappu S, Venkataraman S, Wang X et al. Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz. In 33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024. Institute of Electrical and Electronics Engineers Inc. 2024. (33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024). doi: 10.1109/EPEPS61853.2024.10754397

Peng, Zhekun ; Park, Junyong ; Bandi, Sathvika et al. / Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz. 33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024. Institute of Electrical and Electronics Engineers Inc., 2024. (33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024).

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title = "Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz",

keywords = "2D cross section analysis, ASIC package substrate interconnects, cascaded S-parameters",

author = "Zhekun Peng and Junyong Park and Sathvika Bandi and Santosh Pappu and Srinivas Venkataraman and Xu Wang and Granthana Ranzaswamy and Kim, \{Dong Hyun\}",

note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024 ; Conference date: 06-10-2024 Through 09-10-2024",

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doi = "10.1109/EPEPS61853.2024.10754397",

language = "English",

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AU - Peng, Zhekun

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AU - Pappu, Santosh

AU - Venkataraman, Srinivas

AU - Wang, Xu

AU - Ranzaswamy, Granthana

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KW - ASIC package substrate interconnects

KW - cascaded S-parameters

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UR - https://www.scopus.com/pages/publications/85212672641#tab=citedBy

U2 - 10.1109/EPEPS61853.2024.10754397

DO - 10.1109/EPEPS61853.2024.10754397

M3 - Conference contribution

AN - SCOPUS:85212672641

T3 - 33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024

BT - 33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2024

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Y2 - 6 October 2024 through 9 October 2024

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Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz

Publication series

Conference

ASJC Scopus Subject Areas

Keywords

Access to Document

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