An optimal piece-wise linear strategy for reference voltage variation in time-based CMOS imagers

Xin Qi; John G. Harris

An optimal piece-wise linear strategy for reference voltage variation in time-based CMOS imagers

Xin Qi
, John G. Harris

University of Florida
Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original language	English
Title of host publication	Proceedings of the IASTED International Conference on Circuits, Signals, and Systems
Editors	M.H. Rashid, M.H. Rashid
Pages	182-187
Number of pages	6
State	Published - 2003
Externally published	Yes
Event	Proceedings of the IASTED International Conference on Circuits, Signals and Systems - Cancun, Mexico Duration: May 19 2003 → May 21 2003

Publication series

Name	Proceedings of the IASTED International Conference on Circuits, Signals, and Systems

Conference

Conference	Proceedings of the IASTED International Conference on Circuits, Signals and Systems
Country/Territory	Mexico
City	Cancun
Period	5/19/03 → 5/21/03

ASJC Scopus Subject Areas

General Engineering

Keywords

CMOS image sensor
Comparator delay
Dynamic Range (DR)
Signal-to-Noise Ratio (SNR)
Well Capacity

Cite this

An optimal piece-wise linear strategy for reference voltage variation in time-based CMOS imagers. / Qi, Xin; Harris, John G.
Proceedings of the IASTED International Conference on Circuits, Signals, and Systems. ed. / M.H. Rashid; M.H. Rashid. 2003. p. 182-187 (Proceedings of the IASTED International Conference on Circuits, Signals, and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Qi, X & Harris, JG 2003, An optimal piece-wise linear strategy for reference voltage variation in time-based CMOS imagers. in MH Rashid & MH Rashid (eds), Proceedings of the IASTED International Conference on Circuits, Signals, and Systems. Proceedings of the IASTED International Conference on Circuits, Signals, and Systems, pp. 182-187, Proceedings of the IASTED International Conference on Circuits, Signals and Systems, Cancun, Mexico, 5/19/03.

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title = "An optimal piece-wise linear strategy for reference voltage variation in time-based CMOS imagers",

keywords = "CMOS image sensor, Comparator delay, Dynamic Range (DR), Signal-to-Noise Ratio (SNR), Well Capacity",

author = "Xin Qi and Harris, \{John G.\}",

year = "2003",

language = "English",

isbn = "0889863512",

series = "Proceedings of the IASTED International Conference on Circuits, Signals, and Systems",

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editor = "M.H. Rashid and M.H. Rashid",

booktitle = "Proceedings of the IASTED International Conference on Circuits, Signals, and Systems",

note = "Proceedings of the IASTED International Conference on Circuits, Signals and Systems ; Conference date: 19-05-2003 Through 21-05-2003",

}

TY - GEN

T1 - An optimal piece-wise linear strategy for reference voltage variation in time-based CMOS imagers

AU - Qi, Xin

AU - Harris, John G.

PY - 2003

Y1 - 2003

KW - CMOS image sensor

KW - Comparator delay

KW - Dynamic Range (DR)

KW - Signal-to-Noise Ratio (SNR)

KW - Well Capacity

UR - https://www.scopus.com/pages/publications/1542286819

UR - https://www.scopus.com/pages/publications/1542286819#tab=citedBy

M3 - Conference contribution

AN - SCOPUS:1542286819

SN - 0889863512

SN - 9780889863514

T3 - Proceedings of the IASTED International Conference on Circuits, Signals, and Systems

SP - 182

EP - 187

BT - Proceedings of the IASTED International Conference on Circuits, Signals, and Systems

A2 - Rashid, M.H.

T2 - Proceedings of the IASTED International Conference on Circuits, Signals and Systems

Y2 - 19 May 2003 through 21 May 2003

ER -

An optimal piece-wise linear strategy for reference voltage variation in time-based CMOS imagers

Publication series

Conference

ASJC Scopus Subject Areas

Keywords

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Cite this