Accurate Macro-Modeling for Leakage Current for IDDQ Test

Kyung Ki Kim; Yong-Bin Kim; Minsu Choi; Nohpill Park

doi:10.1109/IMTC.2007.379346

Accurate Macro-Modeling for Leakage Current for I_DDQ Test

Kyung Ki Kim
, Yong-Bin Kim
, Minsu Choi
, Nohpill Park

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

This paper proposes a new precise macro-modeling for leakage current in BSIM4 65nm technology considering subthreshold leakage, gate tunneling leakage, stack effect, and fanout effect. Using the accurate macro-model, a heuristic algorithm is developed to estimate the leakage power and generate input test pattern for minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The experimental result shows that the leakage power estimation using our macro-model is within 5% difference when comparing to Hspice results.

Original language	American English
Journal	Proceedings of the IEEE Instrumentation and Measurement Technology Conference: Synergy of Science and Technology in Measurement (2007, Warsaw, Poland)
DOIs	https://doi.org/10.1109/IMTC.2007.379346
State	Published - May 1 2007

Keywords

Circuit Theory
Computer Simulation
Electron Tunneling
Gate Tunneling Leakage Current
Heuristic Algorithms
IDDQ
IDDQ Testing
Integrated Circuit Modelling
Integrated circuits -- Testing
Leakage Current
Mathematical Models
Power Control
Subthreshold Leakage Current
Test Pattern Generator

Disciplines

Electrical and Computer Engineering

Access to Document

10.1109/IMTC.2007.379346License: Unspecified

Accurate Macro-Modeling for Leakage Current for I sub DDQ sub TFinal published version, 1.53 MBLicense: Unspecified

Cite this

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title = "Accurate Macro-Modeling for Leakage Current for IDDQ Test",

abstract = " This paper proposes a new precise macro-modeling for leakage current in BSIM4 65nm technology considering subthreshold leakage, gate tunneling leakage, stack effect, and fanout effect. Using the accurate macro-model, a heuristic algorithm is developed to estimate the leakage power and generate input test pattern for minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The experimental result shows that the leakage power estimation using our macro-model is within 5\% difference when comparing to Hspice results.",

keywords = "Circuit Theory, Computer Simulation, Electron Tunneling, Gate Tunneling Leakage Current, Heuristic Algorithms, IDDQ, IDDQ Testing, Integrated Circuit Modelling, Integrated circuits -- Testing, Leakage Current, Mathematical Models, Power Control, Subthreshold Leakage Current, Test Pattern Generator",

author = "Kim, \{Kyung Ki\} and Yong-Bin Kim and Minsu Choi and Nohpill Park",

year = "2007",

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language = "American English",

journal = "Proceedings of the IEEE Instrumentation and Measurement Technology Conference: Synergy of Science and Technology in Measurement (2007, Warsaw, Poland)",

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AU - Kim, Yong-Bin

AU - Choi, Minsu

AU - Park, Nohpill

PY - 2007/5/1

Y1 - 2007/5/1

N2 - This paper proposes a new precise macro-modeling for leakage current in BSIM4 65nm technology considering subthreshold leakage, gate tunneling leakage, stack effect, and fanout effect. Using the accurate macro-model, a heuristic algorithm is developed to estimate the leakage power and generate input test pattern for minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The experimental result shows that the leakage power estimation using our macro-model is within 5% difference when comparing to Hspice results.

AB - This paper proposes a new precise macro-modeling for leakage current in BSIM4 65nm technology considering subthreshold leakage, gate tunneling leakage, stack effect, and fanout effect. Using the accurate macro-model, a heuristic algorithm is developed to estimate the leakage power and generate input test pattern for minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The experimental result shows that the leakage power estimation using our macro-model is within 5% difference when comparing to Hspice results.

KW - Circuit Theory

KW - Computer Simulation

KW - Electron Tunneling

KW - Gate Tunneling Leakage Current

KW - Heuristic Algorithms

KW - IDDQ

KW - IDDQ Testing

KW - Integrated Circuit Modelling

KW - Integrated circuits -- Testing

KW - Leakage Current

KW - Mathematical Models

KW - Power Control

KW - Subthreshold Leakage Current

KW - Test Pattern Generator

UR - https://scholarsmine.mst.edu/ele_comeng_facwork/839

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DO - 10.1109/IMTC.2007.379346

M3 - Article

JO - Proceedings of the IEEE Instrumentation and Measurement Technology Conference: Synergy of Science and Technology in Measurement (2007, Warsaw, Poland)

JF - Proceedings of the IEEE Instrumentation and Measurement Technology Conference: Synergy of Science and Technology in Measurement (2007, Warsaw, Poland)

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