A class of systolic multiplier units for VLSI technology

A. R. Hurson; B. Shirazi

doi:10.1007/BF00987038

A class of systolic multiplier units for VLSI technology

A. R. Hurson
, B. Shirazi

Pennsylvania State University
Southern Methodist University

Research output: Contribution to journal › Article › peer-review

Original language	English
Pages (from-to)	261-275
Number of pages	15
Journal	International Journal of Computer & Information Sciences
Volume	14
Issue number	5
DOIs	https://doi.org/10.1007/BF00987038
State	Published - Oct 1985
Externally published	Yes

ASJC Scopus Subject Areas

Theoretical Computer Science
Computational Theory and Mathematics

Keywords

pipeline architecture
Systolic multiplier unit
VLSI design

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10.1007/BF00987038

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title = "A class of systolic multiplier units for VLSI technology",

keywords = "pipeline architecture, Systolic multiplier unit, VLSI design",

author = "Hurson, \{A. R.\} and B. Shirazi",

year = "1985",

month = oct,

doi = "10.1007/BF00987038",

language = "English",

volume = "14",

pages = "261--275",

journal = "International Journal of Computer \& Information Sciences",

issn = "0091-7036",

number = "5",

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AU - Hurson, A. R.

AU - Shirazi, B.

PY - 1985/10

Y1 - 1985/10

KW - pipeline architecture

KW - Systolic multiplier unit

KW - VLSI design

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JO - International Journal of Computer & Information Sciences

JF - International Journal of Computer & Information Sciences

IS - 5

ER -

A class of systolic multiplier units for VLSI technology

ASJC Scopus Subject Areas

Keywords

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